Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-112 Freescale Semiconductor
Table 16-110 describes the fields of the TMR_TEVENT register fields for the timer.
Offset eTSEC1:0x2_4E04 Access: w1c
05678131415
R
—
ETS2 ETS1
—
ALM2 ALM1
W w1c w1c w1c w1c
Reset All zeros
16 23 24 25 26 27 31
R
—
PP1 PP2 PP3
—
W w1c w1c w1c
Reset All zeros
Figure 16-106. TMR_TEVENT Register Definition
Table 16-110. TMR_TEVENT Register Field Descriptions
Bits Name Description
0–5 — Reserved
6 ETS2 External trigger 2 timestamp sampled
0 external trigger timestamp not sampled
1 external trigger timestamp sampled
7 ETS1 External trigger 1 timestamp sampled
0 external trigger timestamp not sampled
1 external trigger timestamp sampled
8–13 — Reserved
14 ALM2 Current time equaled alarm time register 2
0 alarm time has not be reached yet
1 alarm time has been reached
15 ALM1 Current time equaled alarm time register 1
0 alarm time has not be reached yet
1 alarm time has been reached
16–23 — Reserved
24 PP1 Indicates that a periodic pulse has been generated based on FIPER1 register.
0 periodic pulse not generated
1 periodic pulse generated
25 PP2 Indicates that a periodic pulse has been generated based on FIPER2 register.
0 periodic pulse not generated
1 periodic pulse generated
26 PP3 Indicates that a periodic pulse has been generated based on FIPER3 register.
0 periodic pulse not generated
1 periodic pulse generated
27–31 — Reserved