Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-111
16.5.3.10.2 Timer Event Register (TMR_TEVENT)
The eTSEC precision timer implementation can generate additional interrupts that are independent of the
frame based events that controlled via IEVENT. The timer interrupts are not affected by any interrupt
coalescing that may be specified in TXIC/RXIC. Software may poll this register at any time to check for
pending interrupts. If an event occurs and its corresponding enable bit is set in the event mask register
(TEMASK), the event also causes a hardware interrupt at the PIC. A bit in the timer event register is
cleared by writing a 1 to that bit position. Figure 16-4 describes the definition for the TMR_TEVENT
register.
25 CIPH Oscillator input clock phase.
0 non-inverted timer input clock
1 inverted timer input clock (NOTE: this setting is reserved if CKSEL=01.)
26 TMSR Timer soft reset. When enabled, it resets all the timer registers and state machines.
0 normal operation
1 place entire timer in reset except control and config registers
NOTE: Prior to initiating timer reset (setting TMSR), must gracefully stop receiver (See
MACCFG1[RX_EN] description).
User programmable registers are not reset by the soft reset e.g. TMR_CTRL, TMR_TEMASK,
TMR_PEMASK, TMR_ADD, TMR_PRSC, TMROFF_H/L, TMR_ALARMn, and TMR_FIPERn.
27 — Reserved
28 BYP Bypass drift compensated clock
0 64-bit clock counter is incremented on the accumulator overflow
1 64-bit clock counter is directly driven from the external oscillator ignoring accumulator overflow
29 TE 1588 timer enable. If not enabled, all the timer registers and state machines are disabled.
0 timer not enabled
1 timer enabled and resume normal operation
30–31 CKSEL 1588 Timer reference clock source select.
00 External high precision timer reference clock (TSEC_TMR_CLK)
01 eTSEC system clock
10 Reserved
11 RTC clock input Note that the 1588 reference clock must be no slower than 1/7 the Rx_clk
frequency.
The default clock select is eTSEC system clock, which is always active when eTSEC is enabled.
The user must ensure the corresponding clock source is active before changing the 1588 refclk
selection to external reference, RTC, or TX clock. Selecting an inactive 1588 reference clock
may cause boundedly undefined behavior in the ethernet controller and on accesses to the
1588 registers.
Table 16-109. TMR_CTRL Register Field Descriptions (continued)
Bits Name Description