Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-110 Freescale Semiconductor
Table 16-109 describes the fields of the TMR_CTRL register. Register fields not described below are
reserved.
Table 16-109. TMR_CTRL Register Field Descriptions
Bits Name Description
0 ALM1P Alarm1 output polarity
0 active high output
1 active low output
1 ALM2P Alarm2 output polarity
0 active high output
1 active low output
2 — Reserved
3 FS FIPER start indication
0 Fiper is enabled through timer enable
1 Fiper is enabled through timer enable and alarm indication.
4 PP1L Fiper1 pulse loopback mode enabled.
0 Trigger1 input is based upon normal external trigger input.
1 Fiper1 pulse is looped back into Trigger1 input.
5 PP2L Fiper2 pulse loopback mode enabled.
0 Trigger2 input is based upon normal external trigger input.
1 Fiper2 pulse is looped back into Trigger2 input.
6–15 TCLK_
PERIOD
1588 timer reference clock period. The timer clock counter will increment by TCLK_PERIOD every
time the accumulator register overflows. This clock period must be larger than the clock period of
the timer reference clock. For applications where user does not want the clock period to be added,
they can program this field to 1 to count the clock ticks. This field defaulted to 1 to count overflow
ticks.
For nanosecond granularity on 1588 timer counter rate, the TCLK_PERIOD should be calculated
using the following equation:
TCLK_PERIOD = 10
9
/Nominal_Frequency
16 RTPE Record Tx Time-Stamp to PAL Enable.
When set, and FCB[PTP] is set, the 8-byte time-stamp for the packet is written to the PAL located
in external memory location at an offset of 16 bytes from the start of the Data Buffer Pointer of the
first TxBD. For guidelines on using the RTPE bit, refer to Section 16.6.6.5, “Time-Stamp Insertion
on Transmit Packets.”
17 FRD FIPER Realignment Disable
0 Fiper Realignment is enabled.
1 Fiper Realignment is disabled.
18–21 — Reserved
22 ETEP2 External trigger 2 edge polarity
0 Time stamp on the rising edge of the external trigger
1 Time stamp on the falling edge of the external trigger
23 ETEP1 External trigger 1 edge polarity
0 time stamp on the rising edge of the external trigger
1 time stamp on the falling edge of the external trigger
24 COPH Generated clock (TSEC_1588_GCLK) output phase.
0 non-inverted divided clock is output
1 inverted divided clock is output