Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-109
Table 16-108 describes the fields of the RFBPTRn registers.
16.5.3.10 IEEE 1588-Compatible Timestamping Registers
IEEE 1588 compliant timestamping on this device is accomplished using the per-port transmit
timestamping registers within each Ethernet controller memory space (See Section 16.5.3.2.10, “Transmit
Time Stamp Identification Register (TMR_TXTS1–2_ID),” and Section 16.5.3.2.11, “Transmit Time
Stamp Register (TMR_TXTS1–2_H/L)”) in conjunction with the following common registers, which are
located within the memory space for eTSEC1. Because the common 1588 timestamping registers exist
within the eTSEC1 memory space, the eTSEC1 controller must remain enabled in order to use 1588
timestamping for any Ethernet port.
16.5.3.10.1 Timer Control Register (TMR_CTRL)
This register is used to reset, configure, and initialize the eTSEC precision timer clock. The control of all
timer function is performed via programming eTSEC1.The register in eTSEC1 is shared for all eTSECs.
Figure 16-7 describes the definition for the TMR_CTRL register.
Register fields not described below are reserved.
Table 16-108. RFBPTR0–RFBPTR7 Field Descriptions
Bits Name Description
0–28 RFBPTR Pointer to the last free BD in RxBD Ring n. When RBASEn is updated, eTSEC initializes RFBPTRn
to the value in the corresponding RBASEn.
Software may update this register at any time to inform the eTSEC the location of the last free BD in
the ring. Note that the 3 least-significant bits of this register are read only and zero.
29–31 — Reserved.
Offset eTSEC1:0x2_4E00 Access: Mixed
01234 5 6 15
R
ALM1P ALM2P — FS PP1L PP2L TCLK_PERIOD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RTPE FRD — ETEP2 ETEP1 COPH CIPH TMSR — BYP TE CKSEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Figure 16-105. TMR_CTRL Register Definition