Information
Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-108 Freescale Semiconductor
Table 16-107 describes the fields of the RQPRM register.
16.5.3.9.2 Receive Free Buffer Descriptor Pointer Registers 0–7
(RFBPTR0–RFBPTR7)
The RFBPTRn registers specify the location of the last free buffer descriptor in their respective ring. These
registers live in the same 32-bit address space – and must share the same 4 most significant bits – as
RBPTRn. That is, RFBPTRn and its associated RBPTRn must remain in the same 256-Mbyte page. Like
RBPTRn, whenever RBASEn is updated, RFBPTRn is initialized to the value of RBASEn. This indicates
that the ring is completely empty. As buffers are freed and their respective BDs are returned (by setting the
EMPTY bit) to the ring, software is expected to update this register. The eTSEC then performs modulo
arithmetic involving RBASEn, RBPTRn and RFBPTRn to determine the number of free BDs remaining
in the ring. If, at any stage, the value written to RFBPTRn matches that of the respective RBPTRn the
eTSEC free BD calculation assumes that the ring is now completely empty. For more information on the
recommended use of these registers, see Section 16.6.5.1, “Back Pressure Determination through Free
Buffers.” Figure 16-104 describes the definition for the RFBPTRn register.
Offset eTSEC1:0x2_4C00+4n; eTSEC2:0x2_5C00+4n Access: Read/Write
078 31
R
FBTHR LEN
W
Reset All zeros
Figure 16-103. RQPRM Register Definition
Table 16-107. RQPRM Field Descriptions
Bits Name Description
0–7 FBTHR Free BD threshold. Minimum number of BDs required for normal operation. If the eTSEC calculated
number of free BDs drops below this threshold, link layer flow control is asserted.
8–31 LEN Ring length. Total number of Rx BDs in this ring.
Offset eTSEC1:0x2_4C44+8n; eTSEC2:0x2_5C44+8n Access: Read/Write
0 28 29 31
R
RFBPTRn —
W
Reset All zeros
Figure 16-104. RFBPTR0–RFBPTR7 Register Definition