Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-103
16.5.3.6.47 Carry Mask Register 2 (CAM2)
While one of the below mask bits are cleared, the corresponding carry bit in CAR2 is allowed to cause
interrupt indications in register IEVENT[MSR0]. These bits default to a set state. Figure 16-97 describes
the definition for the CAM2 register.
Table 16-101 describes the fields of the CAM2 register.
Offset eTSEC1:0x2_473C; eTSEC2:0x2_573C Access: Read/Write
0 11 12 13 14 15
R
—
M2
TJB
M2
TFC
M2
TCF
M2
TOV
W
Reset0000000000001111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
M2
TUN
M2
TFG
M2
TBY
M2
TPK
M2
TMC
M2
TBC
M2
TPF
M2
TDF
M2
TED
M2
TSC
M2
TMA
M2
TLC
M2
TXC
M2
TNC
—
M2
TDP
W
Reset1111111111111101
Figure 16-97. Carry Mask Register 2 (CAM2) Register Definition
Table 16-101. CAM2 Field Descriptions
Bits Name Description
0–11 — Reserved
12 M2TJB Mask register 2 TJBR counter carry bit mask
13 M2TFC Mask register 2 TFCS counter carry bit mask
14 M2TCF Mask register 2 TXCF counter carry bit mask
15 M2TOV Mask register 2 TOVR counter carry bit mask
16 M2TUN Mask register 2 TUND counter carry bit mask
17 M2TFG Mask register 2 TFRG counter carry bit mask
18 M2TBY Mask register 2 TBYT counter carry bit mask
19 M2TPK Mask register 2 TPKT counter carry bit mask
20 M2TMC Mask register 2 TMCA counter carry bit mask
21 M2TBC Mask register 2 TBCA counter carry bit mask
22 M2TPF Mask register 2 TXPF counter carry bit mask
23 M2TDF Mask register 2 TDFR counter carry bit mask
24 M2TED Mask register 2 TEDF counter carry bit mask
25 M2TSC Mask register 2 TSCL counter carry bit mask
26 M2TMA Mask register 2 TMCL counter carry bit mask
27 M2TLC Mask register 2 TLCL counter carry bit mask
28 M2TXC Mask register 2 TXCL counter carry bit mask
29 M2TNC Mask register 2 TNCL counter carry bit mask