Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-101
16.5.3.6.46 Carry Mask Register 1 (CAM1)
While one of the below mask bits are cleared, the corresponding carry bit in CAR1 is allowed to cause
interrupt indications in register IEVENT[MSR0]. These bits all default to a set state. Figure 16-96
describes the definition for the CAM1 register.
Table 16-100 describes the fields of the CAM1 register.
20 C2TMC Carry register 2 TMCA counter carry bit
21 C2TBC Carry register 2 TBCA counter carry bit
22 C2TPF Carry register 2 TXPF counter carry bit
23 C2TDF Carry register 2 TDFR counter carry bit
24 C2TED Carry register 2 TEDF counter carry bit
25 C2TSC Carry register 2 TSCL counter carry bit
26 C2TMA Carry register 2 TMCL counter carry bit
27 C2TLC Carry register 2 TLCL counter carry bit
28 C2TXC Carry register 2 TXCL counter carry bit
29 C2TNC Carry register 2 TNCL counter carry bit
30 — Reserved, should be cleared
31 C2TDP Carry register 2 TDRP counter carry bit
Offset eTSEC1:0x2_4738; eTSEC2:0x2_5738 Access: Read/Write
01234567 131415
R
M1
64
M1
127
M1
255
M1
511
M1
1K
M1
MAX
M1
MGV
—
M1
REJ
M1
RBY
W
Reset1111111000000011
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
M1
RPK
M1
RFC
M1
RMC
M1
RBC
M1
RXC
M1
RXP
M1
RXU
M1
RAL
M1
RFL
M1
RCD
M1
RCS
M1
RUN
M1
ROV
M1
RFR
M1
RJB
M1
RDR
W
Reset1111111111111111
Figure 16-96. Carry Mask Register 1 (CAM1) Register Definition
Table 16-100. CAM1 Field Descriptions
Bits Name Description
0 M164 Mask register 1 TR64 counter carry bit mask
1 M1127 Mask register 1 TR127 counter carry bit mask
2 M1255 Mask register 1 TR255 counter carry bit mask
3 M1511 Mask register 1 TR511 counter carry bit mask
Table 16-99. CAR2 Field Descriptions (continued)
Bits Name Description