Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-97
16.5.3.6.40 Transmit Control Frame Counter (TXCF)
Figure 16-90 describes the definition for the TXCF register.
Table 16-94 describes the fields of the TXCF register.
16.5.3.6.41 Transmit Oversize Frame Counter (TOVR)
Figure 16-91 describes the definition for the TOVR register.
Table 16-95 describes the fields of the TOVR register.
Offset eTSEC1:0x2_4720; eTSEC2:0x2_5720 Access: Read/Write
0 19 20 31
R
—TXCF
W
Reset All zeros
Figure 16-90. Transmit Control Frame Counter Register Definition
Table 16-94. TXCF Field Descriptions
Bits Name Description
0–19 — Reserved
20–31 TXCF Transmit control frame counter. Increments for every control frame with valid CRC and of lengths 64 to
1518 (non VLAN) or 1522 (VLAN).
Offset eTSEC1:0x2_4724; eTSEC2:0x2_5724 Access: Read/Write
0 19 20 31
R
—TOVR
W
Reset All zeros
Figure 16-91. Transmit Oversized Frame Counter Register Definition
Table 16-95. TOVR Field Descriptions
Bits Name Description
0–19 — Reserved
20–31 TOVR Transmit oversize frame counter. Increments each time a frame is transmitted which exceeds 1518 (non
VLAN) or 1522 (VLAN) with a correct FCS value.