Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-96 Freescale Semiconductor
16.5.3.6.38 Transmit Jabber Frame Counter (TJBR)
Figure 16-88 describes the definition for the TJBR register.
Table 16-92 describes the fields of the TJBR register.
16.5.3.6.39 Transmit FCS Error Counter (TFCS)
Figure 16-89 describes the definition for the TFCS register.
Table 16-93 describes the fields of the TFCS register.
Offset eTSEC1:0x2_4718; eTSEC2:0x2_5718 Access: Read/Write
0 19 20 31
R
— TJBR
W
Reset All zeros
Figure 16-88. Transmit Jabber Frame Counter Register Definition
Table 16-92. TJBR Field Descriptions
Bits Name Description
0–19 — Reserved
20–31 TJBR Transmit jabber frame counter. Increments for each oversized transmitted frame with an incorrect FCS
value.
Offset eTSEC1:0x2_471C; eTSEC2:0x2_571C Access: Read/Write
0 19 20 31
R
—TFCS
W
Reset All zeros
Figure 16-89. Transmit FCS Error Counter Register Definition
Table 16-93. TFCS Field Descriptions
Bits Name Description
0–19 — Reserved
20–31 TFCS Transmit FCS error counter. Increments for every valid sized packet with an incorrect FCS value.