Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-95
16.5.3.6.36 Transmit Total Collision Counter (TNCL)
Figure 16-86 describes the definition for the TNCL register.
Table 16-90 describes the fields of the TNCL register.
16.5.3.6.37 Transmit Drop Frame Counter (TDRP)
Figure 16-87 describes the definition for the TDRP register.
Table 16-91 describes the fields of the TDRP register.
Offset eTSEC1:0x2_470C; eTSEC2:0x2_570C Access: Read/Write
0 19 20 31
R
—TNCL
W
Reset All zeros
Figure 16-86. Transmit Total Collision Counter Register Definition
Table 16-90. TNCL Field Descriptions
Bits Name Description
0–19 — Reserved
20–31 TNCL Transmit total collision counter. Increments by the number of collisions experienced during the transmission
of a frame as defined as the simultaneous presence of signals on the DO and RD circuits (That is,
transmitting and receiving at the same time).
Note: This count does not include collisions that result in an excessive collision condition.
Offset eTSEC1:0x2_4714; eTSEC2:0x2_5714 Access: Read/Write
0151631
R
—TDRP
W
Reset All zeros
Figure 16-87. Transmit Drop Frame Counter Register Definition
Table 16-91. TDRP Field Descriptions
Bits Name Description
0–15 — Reserved
16–31 TDRP Transmit drop frame counter. Increments each time a memory error or an underrun has occurred.