Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-94 Freescale Semiconductor
16.5.3.6.34 Transmit Late Collision Packet Counter (TLCL)
Figure 16-84 describes the definition for the TLCL register.
Table 16-88 describes the fields of the TLCL register.
16.5.3.6.35 Transmit Excessive Collision Packet Counter (TXCL)
Figure 16-85 describes the definition for the TXCL register.
Table 16-89 describes the fields of the TXCL register.
Offset eTSEC1:0x2_4704; eTSEC2:0x2_5704 Access: Read/Write
0 19 20 31
R
—TLCL
W
Reset All zeros
Figure 16-84. Transmit Late Collision Packet Counter Register Definition
Table 16-88. TLCL Field Descriptions
Bits Name Description
0–19 — Reserved
20–31 TLCL Transmit late collision packet counter. Increments for each frame transmitted which experienced a late
collision during a transmission attempt. Late collisions are defined using the collision window field of the
half-duplex [26–31] register.
Offset eTSEC1:0x2_4708; eTSEC2:0x2_5708 Access: Read/Write
0 19 20 31
R
—TXCL
W
Reset All zeros
Figure 16-85. Transmit Excessive Collision Packet Counter Register Definition
Table 16-89. TXCL Field Descriptions
Bits Name Description
0–19 — Reserved
20–31 TXCL Transmit excessive collision packet counter. Increments for each frame that experienced 16 collisions
during transmission and was aborted.