Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-93
16.5.3.6.32 Transmit Single Collision Packet Counter (TSCL)
Figure 16-82 describes the definition for the TSCL register.
Table 16-86 describes the fields of the TSCL register.
16.5.3.6.33 Transmit Multiple Collision Packet Counter (TMCL)
Figure 16-83 describes the definition for the TMCL register.
Table 16-87 describes the fields of the TMCL register.
Offset eTSEC1:0x2_46FC; eTSEC2:0x2_56FC Access: Read/Write
0 19 20 31
R
—TSCL
W
Reset All zeros
Figure 16-82. Transmit Single Collision Packet Counter Register Definition
Table 16-86. TSCL Field Descriptions
Bits Name Description
0–19 — Reserved
20–31 TSCL Transmit single collision packet counter. Increments for each frame transmitted which experienced
exactly one collision during transmission.
Offset eTSEC1:0x2_4700; eTSEC2:0x2_5700 Access: Read/Write
0 19 20 31
R
—TMCL
W
Reset All zeros
Figure 16-83. Transmit Multiple Collision Packet Counter Register Definition
Table 16-87. TMCL Field Descriptions
Bits Name Description
0–19 — Reserved
20–31 TMCL Transmit multiple collision packet counter. Increments for each frame transmitted which experienced 2–15
collisions (including any late collisions) during transmission as defined using the
Half_Duplex[RETRANSMISSION MAXIMUM] field.