Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-91
16.5.3.6.28 Transmit Broadcast Packet Counter (TBCA)
Figure 16-78 describes the definition for the TBCA register.
Table 16-82 describes the fields of the TBCA register.
16.5.3.6.29 Transmit Pause Control Frame Counter (TXPF)
Figure 16-79 describes the definition for the TXPF register.
Table 16-83 describes the fields of the TXPF register.
Offset eTSEC1:0x2_46EC; eTSEC2:0x2_56EC Access: Read/Write
0910 31
R
—TBCA
W
Reset All zeros
Figure 16-78. Transmit Broadcast Packet Counter Register Definition
Table 16-82. TBCA Field Descriptions
Bits Name Description
0–9 — Reserved
10–31 TBCA Transmit broadcast packet counter. Increments for each broadcast frame transmitted (excluding multicast
frames) with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).
Offset eTSEC1:0x2_46F0; eTSEC2:0x2_56F0 Access: Read/Write
0151631
R
— TXPF
W
Reset All zeros
Figure 16-79. Transmit Pause Control Frame Counter Register Definition
Table 16-83. TXPF Field Descriptions
Bits Name Description
0–15 — Reserved
16–31 TXPF Transmit PAUSE frame packet counter. Increments each time a valid PAUSE MAC control frame is
transmitted with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).