Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-90 Freescale Semiconductor
16.5.3.6.26 Transmit Packet Counter (TPKT)
Figure 16-76 describes the definition for the TPKT register.
Table 16-80 describes the fields of the TPKT register.
16.5.3.6.27 Transmit Multicast Packet Counter (TMCA)
Figure 16-77 describes the definition for the TMCA register.
Table 16-81 describes the fields of the TMCA register.
Offset eTSEC1:0x2_46E4; eTSEC2:0x2_56E4 Access: Read/Write
0910 31
R
— TPKT
W
Reset All zeros
Figure 16-76. Transmit Packet Counter Register Definition
Table 16-80. TPKT Field Descriptions
Bits Name Description
0–9 — Reserved
10–31 TPKT Transmit packet counter. Increments for each transmitted packet (including bad packets, excessive deferred
packets, excessive collision packets, late collision packets, all unicast, broadcast, and multicast packets).
Offset eTSEC1:0x2_46E8; eTSEC2:0x2_56E8 Access: Read/Write
0910 31
R
—TMCA
W
Reset All zeros
Figure 16-77. Transmit Multicast Packet Counter Register Definition
Table 16-81. TMCA Field Descriptions
Bits Name Description
0–9 — Reserved
10–31 TMCA Transmit multicast packet counter. Increments for each multicast valid frame transmitted (excluding broadcast
frames) with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).