Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-88 Freescale Semiconductor
16.5.3.6.22 Receive Fragments Counter (RFRG)
Figure 16-72 describes the definition for the RFRG register.
Table 16-76 describes the fields of the RFRG register.
16.5.3.6.23 Receive Jabber Counter (RJBR)
Figure 16-73 describes the definition for the RJBR register.
Table 16-77 describes the fields of the RJBR register.
Offset eTSEC1:0x2_46D4; eTSEC2:0x2_56D4 Access: Read/Write
0151631
R
—RFRG
W
Reset All zeros
Figure 16-72. Receive Fragments Counter Register Definition
Table 16-76. RFRG Field Descriptions
Bits Name Description
0–15 — Reserved
16–31 RFRG Receive fragments counter. Increments for each frame received which is less than 64 bytes in length and
contains an invalid FCS. This includes integral and non-integral lengths.
Offset eTSEC1:0x2_46D8; eTSEC2:0x2_56D8 Access: Read/Write
0151631
R
— RJBR
W
Reset All zeros
Figure 16-73. Receive Jabber Counter Register Definition
Table 16-77. RJBR Field Descriptions
Bits Name Description
0–15 — Reserved
16–31 RJBR Receive jabber counter. Increments for frames received which exceed 1518 (non VLAN) or 1522 (VLAN)
bytes and contain an invalid FCS. This includes alignment errors.