Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-85
16.5.3.6.16 Receive Alignment Error Counter (RALN)
Figure 16-66 describes the definition for the RALN register.
Table 16-70 describes the fields of the RALN register.
16.5.3.6.17 Receive Frame Length Error Counter (RFLR)
Figure 16-67 describes the definition for the RFLR register.
Table 16-71 describes the fields of the RFLR register.
Offset eTSEC1:0x2_46BC; eTSEC2:0x2_56BC Access: Read/Write
0151631
R
—RALN
W
Reset All zeros
Figure 16-66. Receive Alignment Error Counter Register Definition
Table 16-70. RALN Field Descriptions
Bits Name Description
0–15 — Reserved
16–31 RALN Receive alignment error counter. Increments for each received frame from 64 to 1518 (non VLAN) or 1522
(VLAN) which contains an invalid FCS and is not an integral number of bytes.
Offset eTSEC1:0x2_46C0; eTSEC2:0x2_56C0 Access: Read/Write
0151631
R
—RFLR
W
Reset All zeros
Figure 16-67. Receive Frame Length Error Counter Register Definition
Table 16-71. RFLR Field Descriptions
Bits Name Description
0–15 — Reserved
16–31 RFLR Receive frame length error counter. Increments for each frame received in which the 802.3 length field did
not match the number of data bytes actually received (46–1500 bytes). The counter does not increment if
the length field is not a valid 802.3 length, such as an Ethertype value.