Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-84 Freescale Semiconductor
16.5.3.6.14 Receive Pause Frame Packet Counter (RXPF)
Figure 16-64 describes the definition for the RXPF register.
Table 16-68 describes the fields of the RXPF register.
16.5.3.6.15 Receive Unknown Opcode Packet Counter (RXUO)
Figure 16-65 describes the definition for the RXUO register.
Table 16-69 describes the fields of the RXUO register.
Offset eTSEC1:0x2_46B4; eTSEC2:0x2_56B4 Access: Read/Write
0151631
R
— RXPF
W
Reset All zeros
Figure 16-64. Receive Pause Frame Packet Counter Register Definition
Table 16-68. RXPF Field Descriptions
Bits Name Description
0–15 — Reserved
16–31 RXPF Receive PAUSE frame packet counter. Increments each time a PAUSE MAC control frame is received
with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).
Offset eTSEC1:0x2_46B8; eTSEC2:0x2_56B8 Access: Read/Write
0151631
R
—RXUO
W
Reset All zeros
Figure 16-65. Receive Unknown OPCode Packet Counter Register Definition
Table 16-69. RXUO Field Descriptions
Bits Name Description
0–15 — Reserved
16–31 RXUO Receive unknown opcode counter. Increments each time a MAC control frame is received which contains
an opcode other than PAUSE, but the frame has valid CRC and length 64 to 1518 (non VLAN) or 1522
(VLAN).