Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-82 Freescale Semiconductor
Table 16-63 describes the fields of the RPKT register.
16.5.3.6.10 Receive FCS Error Counter (RFCS)
Figure 16-60 describes the definition for the RFCS register.
Table 16-64 describes the fields of the RFCS register.
16.5.3.6.11 Receive Multicast Packet Counter (RMCA)
Figure 16-61 describes the definition for the RMCA register.
Table 16-65 describes the fields of the RMCA register.
Table 16-63. RPKT Field Descriptions
Bits Name Description
0–9 — Reserved
10-31 RPKT Receive packet counter. Increments for each frame received packet (including bad packets, all unicast,
broadcast, and multicast packets).
Offset eTSEC1:0x2_46A4; eTSEC2:0x2_56A4 Access: Read/Write
0151631
R
—RFCS
W
Reset All zeros
Figure 16-60. Receive FCS Error Counter Register Definition
Table 16-64. RFCS Field Descriptions
Bits Name Description
0–15 — Reserved
16–31 RFCS Receive FCS error counter. In Ethernet mode, increments for each frame received that has an integral
64–1518 length and contains a frame check sequence error.
Offset eTSEC1:0x2_46A8; eTSEC2:0x2_56A8 Access: Read/Write
0910 31
R
—RMCA
W
Reset All zeros
Figure 16-61. Receive Multicast Packet Counter Register Definition
Table 16-65. RMCA Field Descriptions
Bits Name Description
0–9 — Reserved
10–31 RMCA Receive multicast packet counter. Increments for each multicast frame with valid CRC and of lengths 64 to
1518 (non VLAN) or 1522 (VLAN), excluding broadcast frames. This count does not include range/length
errors.