Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-81
16.5.3.6.7 Transmit and Receive 1519- to 1522-Byte VLAN Frame Counter (TRMGV)
Figure 16-57 describes the definition for the TRMGV register.
Table 16-61 describes the fields of the TRMGV register.
16.5.3.6.8 Receive Byte Counter (RBYT)
Figure 16-58 shows the RBYT register.
Table 16-62 describes the fields of the RBYT register.
16.5.3.6.9 Receive Packet Counter (RPKT)
Figure 16-59 describes the definition for the RPKT register.
Offset eTSEC1:0x2_4698; eTSEC2:0x2_5698 Access: Read/Write
0910 31
R
—TRMGV
W
Reset All zeros
Figure 16-57. Transmit and Received 1519- to 1522-Byte VLAN Frame Register Definition
Table 16-61. TRMGV Field Descriptions
Bits Name Description
0–9 — Reserved
10–31 TRMGV Increments for each good or bad frame transmitted and received which is 1519–1522 bytes in length,
inclusive (excluding preamble and SFD but including FCS bytes).
Offset eTSEC1:0x2_469C; eTSEC2:0x2_569C Access: Read/Write
0 31
R
RBYT
W
Reset All zeros
Figure 16-58. Receive Byte Counter Register Definition
Table 16-62. RBYT Field Descriptions
Bits Name Description
0–31 RBYT Receive byte counter. The statistic counter register increments by the byte count of frames received, including
those in bad packets, excluding preamble and SFD but including FCS bytes.
Offset eTSEC1:0x2_46A0; eTSEC2:0x2_56A0 Access: Read/Write
0910 31
R
— RPKT
W
Reset All zeros
Figure 16-59. Receive Packet Counter Register Definition