Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-80 Freescale Semiconductor
16.5.3.6.5 Transmit and Receive 512- to 1023-Byte Frame Counter (TR1K)
Figure 16-55 shows the TR1K register.
Table 16-59 describes the fields of the TR1K register.
16.5.3.6.6 Transmit and Receive 1024- to 1518-Byte Frame Counter (TRMAX)
Figure 16-56 describes the definition for the TRMAX register.
Table 16-60 describes the fields of the TRMAX register.
Offset eTSEC1:0x2_4690; eTSEC2:0x2_5690 Access: Read/Write
0910 31
R
—TR1K
W
Reset All zeros
Figure 16-55. Transmit and Received 512- to 1023-Byte Frame Register Definition
Table 16-59. TR1K Field Descriptions
Bits Name Description
0–9 — Reserved
10–31 TR1K Increments for each good or bad frame transmitted and received which is 512–1023 bytes in length, inclusive
(excluding preamble and SFD but including FCS bytes).
Offset eTSEC1:0x2_4694; eTSEC2:0x2_5694 Access: Read/Write
0910 31
R
—TRMAX
W
Reset All zeros
Figure 16-56. Transmit and Received 1024- to 1518-Byte Frame Register Definition
Table 16-60. TRMAX Field Descriptions
Bits Name Description
0–9 — Reserved
10–31 TRMAX Increments for each good or bad frame transmitted and received which is 1024–1518 bytes in length,
inclusive (excluding preamble and SFD but including FCS bytes).