Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-79
16.5.3.6.3 Transmit and Receive 128- to 255-Byte Frame Counter (TR255)
Figure 16-53 describes the definition for the TR255 register.
Table 16-57 describes the fields of the TR255 register.
16.5.3.6.4 Transmit and Receive 256- to 511-Byte Frame Counter (TR511)
Figure 16-54 describes the definition for the TR511 register.
Table 16-58 describes the fields of the TR511 register.
Offset eTSEC1:0x2_4688; eTSEC2:0x2_5688 Access: Read/Write
0910 31
R
—TR255
W
Reset All zeros
Figure 16-53. Transmit and Received 128- to 255-Byte Frame Register Definition
Table 16-57. TR255 Field Descriptions
Bits Name Description
0–9 — Reserved
10–31 TR255 Transmit and receive 128- to 255-byte frame counter—Increments for each good or bad frame transmitted and
received which is 128–255 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes).
Offset eTSEC1:0x2_468C; eTSEC2:0x2_568C Access: Read/Write
0910 31
R
—TR511
W
Reset All zeros
Figure 16-54. Transmit and Received 256- to 511-Byte Frame Register Definition
Table 16-58. TR511 Field Descriptions
Bits Name Description
0–9 — Reserved
10–31 TR511 Increments for each good or bad frame transmitted and received which is 256–511 bytes in length, inclusive
(excluding preamble and SFD but including FCS bytes).