Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-78 Freescale Semiconductor
16.5.3.6.1 Transmit and Receive 64-Byte Frame Counter (TR64)
Figure 16-51 describes the definition for the TR64 register.
Table 16-55 describes the fields of the TR64 register.
16.5.3.6.2 Transmit and Receive 65- to 127-Byte Frame Counter (TR127)
Figure 16-52 describes the definition for the TR127 register.
Table 16-56 describes the fields of the TR127 register.
Offset eTSEC1:0x2_4680; eTSEC2:0x2_5680 Access: Read/Write
0910 31
R
—TR64
W
Reset All zeros
Figure 16-51. Transmit and Receive 64-Byte Frame Register Definition
Table 16-55. TR64 Field Descriptions
Bits Name Description
0–9 — Reserved
10–31 TR64 Transmit and receive 64-byte frame counter—Increment for each good or bad frame transmitted and received
which is 64 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes).
Offset eTSEC1:0x2_4684; eTSEC2:0x2_5684 Access: Read/Write
0910 31
R
—TR127
W
Reset All zeros
Figure 16-52. Transmit and Receive 65- to 127-Byte Frame Register Definition
Table 16-56. TR127 Field Descriptions
Bits Name Description
0–9 — Reserved
10–31 TR127 Transmit and receive 65- to 127-byte frame counter—Increments for each good or bad frame transmitted and
received which is 65–127 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes).