Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-77
Table 16-54 describes the fields of a MACxADDR2 register.
16.5.3.6 MIB Registers
This section describes the MIB registers. The eTSEC RMON module has separate statistics counters,
which simply count or accumulate statistical events that occur as packets transmitted and received. These
counters support RMON MIB group 1, RMON MIB group 2 if table counters, RMON MIB group 3,
RMON MIB group 9, RMON MIB 2, and the IEEE 802.3 Ethernet MIB.
An interrupt can be generated upon any one counter’s rollover condition through a carry interrupt output
from the RMON. Each counter’s rollover condition can be discretely masked from causing an interrupt by
internal masking registers. In addition, each individual counter value may be reset on read access, or all
counters may be simultaneously reset by setting ECNTRL[CLRCNT].
The majority of MIB counters are Ethernet-specific.
NOTE
RMON counters do not comprehend custom VLAN tagged frames.
Affected counters include TRMGV, RMCA, RBCA, RXCF, RXPF, RXUO,
RALN, RFLR, ROVR, RJBR, TMCA, TBCA, TXPF, TXCF. Specifically,
custom VLAN tagged frames are not afforded the ability to be greater than
1518, as compared to the IEEE standard tagged frames.
NOTE
The transmit and receive frame counters (TR64, TR127, TR 255, TR511,
TR1K, TRMAX, adn TRMGV) do not increment for aborted frames
(collision retry limit exceeded, late collision, underrun, EBERR, TxFIFO
data error, frame truncated due to exceeding MAXFRM, or excessive
deferral).
Table 16-54. MAC01ADDR2–MAC15ADDR2 Field Descriptions
Bit Name Description
0–7 Exact Match Address, 2nd Octet This field holds the second octet of the exact match address. The second
octet (destination address bits 8–15) defaults to a value of 0x0.
8–15 Exact Match Address, 1st Octet This field holds the first octet of the exact match address. The first octet
(destination address bits 0–7) defaults to a value of 0x0.
16–31 — Reserved