Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-76 Freescale Semiconductor
For any valid, non-zero MAC address received, exact match registers can be excluded individually by
clearing them to all zero bytes.
Table 16-53 describes the fields of a MACnADDR1 register.
16.5.3.5.16 MAC Exact Match Address 1–15 Part 2 Registers
(MAC01ADDR2–MAC15ADDR2)
The MAC01ADDR2–MAC15ADDR2 registers are written by the user with the unicast or multicast
addresses aliasing the MAC. Figure 16-50 describes the definition for all of the fifteen MACxADDR2
registers.
Offset eTSEC1:0x2_4548+8n; eTSEC2:0x2_5548+8n Access: Read/Write
0 7 8 1516 2324 31
R
Exact Match Address,
6th Octet
Exact Match Address,
5th Octet
Exact Match Address,
4th Octet
Exact Match Address,
3rd Octet
W
Reset All zeros
Figure 16-49. MAC Exact Match Address n Part 1 Register Definition
Table 16-53. MACnADDR1 Field Descriptions
Bit Name Description
0–7 Exact Match Address, 6th Octet Holds the sixth octet of the exact match address. The sixth octet (destination
address bits 40
–47) defaults to a value of 0x0.
8–15 Exact Match Address, 5th Octet Holds the fifth octet of the exact match address. The fifth octet (destination
address bits 32–39) defaults to a value of 0x0.
16–23 Exact Match Address, 4th Octet Holds the fourth octet of the exact match address. The fourth octet (destination
address bits 24–31) defaults to a value of 0x0.
24–31 Exact Match Address, 3rd Octet Holds the third octet of the exact match address. The third octet (destination
address bits 16
–23) defaults to a value of 0x0.
Offset eTSEC1:0x2_454C+8n; eTSEC2:0x2_554C+8n Access: Read/Write
0781516 31
R
Exact Match Address,
2nd Octet
Exact Match Address,
1st Octet
—
W
Reset All zeros
Figure 16-50. MAC Exact Match Address x Part 2 Register Definition