Information

Signal Descriptions
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
2-14 Freescale Semiconductor
MCKE DDR clock enable Driven Low
MCK[0:2] DDR differential clocks Low
MCK
[0:2] DDR differential clocks Low
MODT[0:1] DRAM on-die termination Driven Low
UART_SOUT[1:2] DUART serial data out High-Z
LA[0:25] LBC port address Active—used to load reset configuration
word
LCS[0] LBC chip select 0 Active—used to load reset configuration
word
LCS[1:3] LBC chip select High
LWE[0:1] LBC write enable High
LBCTL LBC data buffer control Active—used to load reset configuration
word
LOE
/LGPL2 LBC output enable/GP line 2 Active—used to load reset configuration
word
LCLK0 LBC clock 0 High-Z
LGPL[0:1], LGPL[3:5] LBC UPM General purpose line High
TSEC1_MDC Ethernet management data clock Low
TSEC1_GTX_CLK eTSEC1 transmit clock out Low
TSEC1_TXD[3:0] eTSEC1 transmit data 3–0 Low
TSEC1_TX_EN eTSEC1 transmit enable Low
TSEC1_TX_ER eTSEC1 transmit error Low
TSEC2_TXD[3:0] eTSEC2 transmit data 3–0 Low
TSEC2_TX_EN eTSEC2 transmit enable Low
TSEC2_TX_ER eTSEC2 transmit error Low
TSEC_TMR_GCLK 1588 clock-out Low
TSEC_TMR_PP[1:3] 1588 timer pulse-out 1, 2, 3 Low
TSEC_TMR_ALARM[1:2] 1588 timer alarm-out 1, 2 Low
SD_CLK eSDHC clock out Low
SD_PLL_TPD Digital test point for SerDes PLL testing High
TDO Test data out High-Z
QUIESCE
Quiescent state High
GTM1_TOUT[3:4] Timer out 3, 4 High
Table 2-2. Output Signal States During System Reset (continued)
Interface Signal State During Reset