Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-75
16.5.3.5.14 MAC Station Address Part 2 Register (MACSTNADDR2)
The MACSTNADDR2 register is written by the user. Figure 16-48 describes the definition for the
MACSTNADDR2 register.
Table 16-52 describes the fields of the MACSTNADDR2 register.
16.5.3.5.15 MAC Exact Match Address 1–15 Part 1 Registers
(MAC01ADDR1–MAC15ADDR1)
The MAC01ADDR1–MAC15ADDR1 registers are written by the user with the unicast or multicast
addresses aliasing the MAC. Figure 16-49 describes the definition for all of the fifteen MACnADDR1
registers. The value of the address written into MACxADDR1 and MACnADDR2 is byte reversed from
how it would appear in the DA field of a frame in memory. For example, for a MAC address of
0x1234_5678_ABCD, MACnADDR1 is set to 0xCDAB_7856 and MACnADDR2 is set to 0x3412_0000.
16–23 Station Address, 4th Octet This field holds the fourth octet of the station address. The fourth octet
(station address bits 24
–31) defaults to a value of 0x0.
24–31 Station Address, 3rd Octet This field holds the third octet of the station address. The third octet (station
address bits 16–23) defaults to a value of 0x0.
Offset eTSEC1:0x2_4544; eTSEC2:0x2_5544 Access: Read/Write
0781516 31
R
Station Address, 2nd Octet Station Address, 1st Octet
—
W
Reset All zeros
Figure 16-48. MAC Station Address Part 2 Register Definition
Table 16-52. MACSTNADDR2 Field Descriptions
Bit Name Description
0–7 Station Address, 2nd Octet This field holds the second octet of the station address. The second octet
(station address bits 8
–15) defaults to a value of 0x0.
8–15 Station Address, 1st Octet This field holds the first octet of the station address. The first octet (station
address bits 0–7) defaults to a value of 0x0.
16–31 — Reserved
Table 16-51. MACSTNADDR1 Field Descriptions (continued)
Bit Name Description