Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-74 Freescale Semiconductor
16.5.3.5.12 Interface Status Register (IFSTAT)
Figure 16-46 shows the IFSTAT register.
Table 16-50 describes the fields of the FSTAT register.
16.5.3.5.13 MAC Station Address Part 1 Register (MACSTNADDR1)
The MACSTNADDR1 register is written by the user. The value of the station address written into
MACSTNADDR1 and MACSTNADDR2 is byte reversed from how it would appear in the DA field of a
frame in memory. For example, for a station address of 0x1234_5678_ABCD, MACSTNADDR1 is set to
0xCDAB_7856 and MACSTNADDR2 is set to 0x3412_0000.
Figure 16-47 shows the MACSTNADDR1 register.
Table 16-51 describes the fields of the MACSTNADDR1 register.
Offset eTSEC1:0x2_453C; eTSEC2:0x2_553C Access: Read only
0 21 22 23 31
R
—
Excess Defer
—
W
Reset All zeros
Figure 16-46. Interface Status Register Definition
Table 16-50. IFSTAT Field Descriptions
Bits Name Description
0–21 — Reserved
22 Excess Defer Excessive transmission defer. This bit latches high and is cleared when read. This bit is cleared by
default.
0 Normal operation.
1 The MAC excessively defers a transmission.
23–31 — Reserved
Offset eTSEC1:0x2_4540; eTSEC2:0x2_5540 Access: Read/Write
0 7 8 1516 2324 31
R
Station Address, 6th Octet Station Address, 5th Octet Station Address, 4th Octet Station Address, 3rd Octet
W
Reset All zeros
Figure 16-47. MAC Station Address Part 1 Register Definition
Table 16-51. MACSTNADDR1 Field Descriptions
Bit Name Description
0–7 Station Address, 6th Octet This field holds the sixth octet of the station address. The sixth octet (station
address bits 40
–47) defaults to a value of 0x0.
8–15 Station Address, 5th Octet This field holds the fifth octet of the station address. The fifth octet (station
address bits 32–39) defaults to a value of 0x0.