Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-72 Freescale Semiconductor
16.5.3.5.8 MII Management Address Register (MIIMADD)
The MIIMADD register is written by the user. Figure 16-42 shows the MIIMADD register.
Table 16-46 describes the fields of the MIIMADD register.
16.5.3.5.9 MII Management Control Register (MIIMCON)
MIIMCON, shown in Figure 16-43, is written by the user.
Table 16-47 describes the fields of the MIIMCON register.
Offset eTSEC1:0x2_4528 Access: Read/Write
0 18 19 23 24 26 27 31
R
— PHY Address —
Register
Address
W
Reset All zeros
Figure 16-42. MIIMADD Register Definition
Table 16-46. MIIMADD Field Descriptions
Bits Name Description
0–18 — Reserved
19–23 PHY Address This field represents the 5-bit PHY address field of Mgmt cycles. Up to 31 PHYs can be addressed
(0 is reserved). Its default value is 0x00.
24–26 — Reserved
27–31 Register Address This field represents the 5-bit register address field of Mgmt cycles. Up to 32 registers can be
accessed. Its default value is 0x00.
Offset eTSEC1:0x2_452C Access: WO
0151631
R
—
W PHY Control
Reset All zeros
Figure 16-43. MII Mgmt Control Register Definition
Table 16-47. MIIMCON Field Descriptions
Bits Name Description
0–15 — Reserved
16–31 PHY Control If written, an MII Mgmt write cycle is performed using this 16-bit data, the pre-configured PHY address
(at MIIMADD[PHY Address]) and the register address (at MIIMADD[Register Address]). Its default
value is 0x0000.