Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-71
16.5.3.5.7 MII Management Command Register (MIIMCOM)
The MIIMCOM register is written by the user. Figure 16-41 describes the definition for MIIMCOM.
Table 16-45 describes the fields of the MIIMCOM register.
27 No Pre Preamble suppress. This bit is cleared by default.
0 The MII MGMT performs Mgmt read/write cycles with 32 clocks of preamble.
1 The MII MGMT suppresses preamble generation and reduces the Mgmt cycle from 64 clocks to 32
clocks. This is in accordance with IEEE 802.3/22.2.4.4.2.
28 — Reserved
29–31 MgmtClk This field determines the clock frequency of the MII management clock (TSEC_MDC). Its default value
is 111.
000 1/4 of the eTSEC system clock divided by 8
001 1/4 of the eTSEC system clock divided by 8
010 1/6 of the eTSEC system clock divided by 8
011 1/8 of the eTSEC system clock divided by 8
100 1/10 of the eTSEC system clock divided by 8
101 1/14 of the eTSEC system clock divided by 8
110 1/20 of the eTSEC system clock divided by 8
111 1/28 of the eTSEC system clock divided by 8
Offset eTSEC1:0x2_4524 Access: Read/Write
0 29 30 31
R
— Scan Cycle Read Cycle
W
Reset All zeros
Figure 16-41. MIIMCOM Register Definition
Table 16-45. MIIMCOM Descriptions
Bits Name Description
0–29 — Reserved
30 Scan Cycle Scan cycle. This bit is cleared by default.
0 Normal operation.
1 The MII management continuously performs read cycles. This is useful for monitoring link fail, for
example.
31 Read Cycle Read cycle. This bit is cleared by default but is not self-clearing once set.
0 Normal operation.
1 The MII management performs a single read cycle upon the transition of this bit from 0 to 1 using the
PHY address (at MIIMADD[PHY Address]) and the register address (at MIIMADD[Register
Address]). The 0-to-1 transition of this bit also causes the MIIMIND[Busy] bit to be set. The read is
complete when the MIIMIND[Busy] bit clears. Data is returned in register MIIMSTAT[PHY Status].
Table 16-44. MIIMCFG Field Descriptions (continued)
Bits Name Description