Information
Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-70 Freescale Semiconductor
16.5.3.5.5 Maximum Frame Length Register (MAXFRM)
The MAXFRM register is written by the user. Figure 16-39 shows the MAXFRM register.
Table 16-43 describes the fields of the MAXFRM register.
16.5.3.5.6 MII Management Configuration Register (MIIMCFG)
The MIIMCFG register is written by the user to configure all MII management operations. Note that MII
management hardware is shared by all eTSECs. Thus, only through the MIIM registers of eTSEC1 can
external PHYs be accessed and configured.
Figure 16-40 describes the definition for the MIIMCFG register.
Table 16-44 describes the fields of the MIIMCFG register.
Offset eTSEC1:0x2_4510; eTSEC2:0x2_5510 Access: Read/Write
0151631
R
— Maximum Frame
W
Reset00000000000000000000011000000000
Figure 16-39. Maximum Frame Length Register Definition
Table 16-43. MAXFRM Field Descriptions
Bits Name Description
0–15 — Reserved
16–31 Maximum Frame This field is set to 0x0600 (1536 bytes) by default and always must be set to a value greater than or
equal to 0x0040 (64 bytes), but not greater than 0x2580 (9600 bytes). It sets the maximum Ethernet
frame size in both the transmit and receive directions. (Refer to MACCFG2[Huge Frame].)
Note that if MACCFG2[Huge Frame] = 0, the value of this field must be less than or equal to
MRBLR[MRBL] (minimum number of RxBDs per ring). See Section 16.5.3.5.2, “MAC
Configuration 2 Register (MACCFG2),” Section 16.5.3.3.9, “Maximum Receive Buffer Length
Register (MRBLR),” and Section 16.6.7.3, “Receive Buffer Descriptors (RxBD).”
Offset eTSEC1:0x2_4520 Access: Read/Write
01 26 27 28 29 31
R
Reset Mgmt — No Pre — MgmtClk
W
Reset 0 00000000000000000000000000 0 0111
Figure 16-40. MII Management Configuration Register Definition
Table 16-44. MIIMCFG Field Descriptions
Bits Name Description
0 Reset Mgmt Reset management. This bit is cleared by default.
0 Allow the MII MGMT to perform mgmt read/write cycles if requested through the host interface.
1 Reset the MII MGMT.
1–26 — Reserved