Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-68 Freescale Semiconductor
16.5.3.5.3 Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG)
The IPGIFG register is written by the user. Figure 16-37 describes the definition for IPGIFG.
Table 16-41 describes the fields of the IPGIFG register.
Offset eTSEC1:0x2_4508; eTSEC2:0x2_5508 Access: Read/Write
0 1 7 8 9 15 16 23 24 25 31
R
—
Non-Back-to-Back
Inter-Packet-Gap, Part 1
—
Non-Back-to-Back
Inter-Packet-Gap, Part 2
Minimum IFG
Enforcement
—
Back-to-Back
Inter-Packet-Gap
W
Reset01000000011000000101000001100000
Figure 16-37. IPGIFG Register Definition
Table 16-41. IPGIFG Field Descriptions
Bits Name Description
0—Reserved
1–7 Non-Back-to-Back
Inter-Packet-Gap, Part 1
This is a programmable field representing the optional carrier sense window referenced in
IEEE 802.3/4.2.3.2.1 “carrier deference.” If carrier is detected during the timing of IPGR1,
the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC
continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair
access to medium. Its range of values is 0x00 to IPGR2. Its default is 0x40 (64d) which
follows the two-thirds/one-third guideline.
8—Reserved
9–15 Non-Back-to-Back
Inter-Packet-Gap, Part 2
This is a programmable field representing the non-back-to-back inter-packet-gap in bits. Its
default is 0x60 (96d), which represents the minimum IPG of 96 bits.
16–23 Minimum IFG
Enforcement
This is a programmable field representing the minimum number of bits of IFG to enforce
between frames. A frame is dropped whose IFG is less than that programmed. The default
setting of 0x50 (80d) represents half of the nominal minimum IFG which is 160 bits.
24 — Reserved
25–31 Back-to-Back
Inter-Packet-Gap
This is a programmable field representing the IPG between back-to-back packets. This is
the IPG parameter used exclusively in full-duplex mode and in half-duplex mode if two
transmit packets are sent back-to-back. Set this field to the number of bits of IPG desired.
The default setting of 0x60 (96d) represents the minimum IPG of 96 bits.