Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-67
26 Huge
Frame
Huge frame enable. This bit is cleared by default.
0 Limit the length of frames received to less than or equal to the maximum frame length value
(MAXFRM[Maximum Frame]) and limit the length of frames transmitted to less than the maximum
frame length.
See Section 16.6.7, “Buffer Descriptors,” for further details of buffer descriptor bit updating.
Frame type Frame length
Packet
truncation
Buffer descriptor
updated
Receive or transmit > maximum frame length yes yes
Receive = maximum frame length no no
Transmit = maximum frame length no yes
Receive or transmit < maximum frame length no no
1 Frames are transmitted and received regardless of their relationship to the maximum frame length.
Note that if Huge Frame is cleared, the user must ensure that adequate buffer space is allocated for
received frames. See Section 16.5.3.5.5, “Maximum Frame Length Register (MAXFRM),” for further
information.
27 Length
check
Length check. This bit is cleared by default.
0 No length field checking is performed.
1 The MAC checks the frame’s length field on receive to ensure it matches the actual data field length.
Transmitted frames are not checked.
28 — Reserved
29 PAD/CRC Pad and append CRC. This bit is cleared by default. This bit must be set when in half-duplex mode
(MACCFG2[Full Duplex] is cleared).
0 Frames presented to the MAC have a valid length and contain a CRC.
1 The MAC pads all transmitted short frames and appends a CRC to every frame regardless of
padding requirement.
30 CRC EN CRC enable. If the configuration bit PAD/CRC ENABLE or the per-packet PAD/CRC ENABLE is set,
CRC ENABLE is ignored. This bit is cleared by default.
0 Frames presented to the MAC have a valid length and contain a valid CRC.
1 The MAC appends a CRC on all frames. Clear this bit if frames presented to the MAC have a valid
length and contain a valid CRC.
31 Full
Duplex
Full duplex configure. This bit is cleared by default.
0 The MAC operates in half-duplex mode only.
1 The MAC operates in full-duplex mode.
Table 16-40. MACCFG2 Field Descriptions (continued)
Bits Name Description