Information

Signal Descriptions
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 2-13
2.2 Output Signal States During Reset
When a system reset is recognized (PORESET or HRESET are asserted), the device aborts all current
internal and external transactions (with the exception of RTC) and releases all bidirectional I/O signals to
a high-impedance state. See Chapter 4, “Reset, Clocking, and Initialization,” for a complete description of
the reset functionality.
During reset, the device ignores most input signals (except for the reset configuration signals) and drives
most of the output-only signals to an inactive state. Table 2-2 shows the states of the output-only signals.
GTM1_TOUT[3:4] Timer out 3, 4 Global
Timers
2 I/O 5-53/5-56 GPIO[9:10] 21-1/21-2
GTM1_TIN4 Timer in 4 Global
Timers
1 I 5-53/5-56 — —
GTM1_TGATE4 Timer gate 4 Global
Timers
1 I 5-53/5-56 GPIO[15] 21-1/21-2
MSRCID0/LSRCID0 Memory debug
source ID
Debug 1 O —,
10-2/10-5
UART_SOUT[1] 18-1/18-3
MSRCID1/LSRCID1 Memory debug
source ID
Debug 1 O —,
10-2/10-5
UART_SIN[1] 18-1/18-3
MSRCID2/LSRCID2 Memory debug
source ID
Debug 1 O —,
10-2/10-5
UART_SOUT[2] 18-1/18-3
MSRCID3/LSRCID3 Memory debug
source ID
Debug 1 O —,
10-2/10-5
UART_SIN[2] 18-1/18-3
MSRCID4/LSRCID4 Memory debug
source ID
Debug 1 O —,
10-2/10-5
SPIMOSI 19-1/19-6
MDVAL/LDVAL Memory debug
data valid
Debug 1 O —,
10-2/10-5
SPIMISO 19-1/19-6
Table 2-2. Output Signal States During System Reset
Interface Signal State During Reset
MDM[0:3] DDR data mask High-Z
MDM[8] DDR data mask High-Z
MBA[2:0] DDR bank select High-Z
MA[13:0] DDR address High-Z
MWE
DDR write enable High-Z
MRAS
DDR row address strobe High-Z
MCAS DDR column address strobe High-Z
MCS[0:1] DDR chip select (2/DIMM) High-Z
Table 2-1. MPC8308 Signal Reference by Functional Block (continued)
Name Description
Functional
Block
No. of
Signals
I/O
Table/
Page
Alternate
Function(s)
Table/
Page