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ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller MAPBGA 473 (19x19) MPC83xx 32-Bit Single-Core 333 MHz
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Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-65
15 Reset Tx Fun Reset transmit function block. This bit is cleared by default.
0 Normal operation.
1 Place the transmit function in reset. This block performs the frame transmission protocol.
16–22 — Reserved
23 Loop Back Loop back. This bit is cleared by default.
0 Normal operation.
1 Loop back the MAC transmit outputs to the MAC receive inputs.
24–25 — Reserved
26 Rx_Flow Receive flow. This bit is cleared by default.
Must be 0 if MACCFG2[Full Duplex] = 0.
0 The receive MAC control ignores PAUSE flow control frames.
1 The receive MAC control detects and acts on PAUSE flow control frames.
Note: Should not be set when operating in Half-Duplex mode
27 Tx_Flow Transmit flow. This bit is cleared by default.
Must be 0 if MACCFG2[Full Duplex] = 0.
0 The transmit MAC control may not send PAUSE flow control frames if requested by the system.
Note: 1The transmit MAC control may send PAUSE flow control frames if requested by the
system.Should not be set when operating in Half-Duplex mode
28 Sync’d Rx EN Receive enable synchronized to the receive stream. (Read-only)
0 Frame reception is not enabled.
1 Frame reception is enabled.
29 Rx_EN Receive enable. This bit is cleared by default. If set, prior to clearing this bit, set DMACTRL[GRS] then
confirm subsequent occurrence of the graceful receive stop interrupt (IEVENT[GRSC] is set).
0 The MAC may not receive frames from the PHY.
1 The MAC may receive frames from the PHY.
30 Sync’d Tx EN Transmit enable synchronized to the transmit stream. (Read-only)
0 Frame transmission is not enabled.
1 Frame transmission is enabled.
31 Tx_EN Transmit enable. This bit is cleared by default. If set, prior to clearing this bit, set DMACTRL[GTS] then
confirm subsequent occurrence of the graceful receive stop interrupt (IEVENT[GTSC] is set).
0 The MAC may not transmit frames from the system.
1 The MAC may transmit frames from the system.
Table 16-39. MACCFG1 Field Descriptions (continued)
Bits Name Description