Information
Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-64 Freescale Semiconductor
Yet another parameter that can be modified through the MII registers is the length of the MII management
interface preamble. After establishing that a PHY supports preamble suppression, the host may so
configure the eTSEC. While enabled, the length of MII management frames are reduced from 64 clocks
to 32 clocks. This effectively doubles the efficiency of the interface.
16.5.3.5 MAC Registers
This section describes the MAC registers.
16.5.3.5.1 MAC Configuration 1 Register (MACCFG1)
MACCFG1 is written by the user. Figure 16-35 describes the definition for the MACCFG1 register.
Table 16-39 describes the fields of the MACCFG1 register.
\
Offset eTSEC1:0x2_4500; eTSEC2:0x2_5500 Access: Mixed
0 1 11 12 13 14 15
R
Soft_Reset — Reset Rx MC Reset Tx MC Reset Rx Fun Reset Tx Fun
W
Reset All zeros
16 22 23 24 25 26 27 28 29 30 31
R
— Loop Back — Rx_Flow Tx_Flow
Sync’d Rx EN
Rx_EN
Sync’d Tx EN
Tx_EN
W
Reset All zeros
Figure 16-35. MACCFG1 Register Definition
Table 16-39. MACCFG1 Field Descriptions
Bits Name Description
0 Soft_Reset Soft reset. This bit is cleared by default. See Section 16.6.2.2, “Soft Reset and Reconfiguring
Procedure,” for more information on setting this bit.
0 Normal operation.
1 Place the entire MAC in reset except for the host interface.
1–11 — Reserved
12 Reset Rx MC Reset receive MAC control block. This bit is cleared by default.
0 Normal operation.
1 Place the receive part of the MAC in reset. This block detects control frames and contains the pause
timers.
13 Reset Tx MC Reset transmit MAC control block. This bit is cleared by default.
0 Normal operation.
1 Place the transmit part of the MAC in reset. This block multiplexes data and control frame transfers.
It also responds to XOFF PAUSE control frames.
14 Reset Rx Fun Reset receive function block. This bit is cleared by default.
0 Normal operation.
1 Place the receive function in reset. This block performs the receive frame protocol.