Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-62 Freescale Semiconductor
programmable register set, the pad/CRC behavior can be dynamically adjusted on a per-packet
basis.
16.5.3.4.2 Controlling CSMA/CD
The half-duplex register (HAFDUP) allows control over the carrier-sense multiple access/collision
detection (CSMA/CD) logic of the eTSEC. Half-duplex mode is only supported for 10- and 100-Mbps
operation. Following the completion of the packet transmission the part begins timing the inter packet gap
(IPG) as programmed in the back-to-back IPG configuration register. The system is now free to begin
another frame transfer.
In full-duplex mode both the carrier sense (CRS) and collision (COL) indications from the PHY are
ignored, but in half-duplex mode the eTSEC defers to CRS, and following a carrier event, times the IPG
using the non-back-to-back IPG configuration values that include support for the optional
two-thirds/one-third CRS deferral process. This optional IPG mechanism enhances system robustness and
ensures fair access to the medium. During the first two-thirds of the IPG, the IPG timer is cleared if CRS
is sensed. During the final one-third of the IPG, CRS is ignored and the transmission begins once IPG is
timed. The two-thirds/one-third ratio is the recommended value.
16.5.3.4.3 Handling Packet Collisions
While transmitting a packet in half-duplex mode, the eTSEC is sensitive to COL. If a collision occurs, it
aborts the packet and outputs the 32-bit jam sequence. The jam sequence is comprised of several bits of
the CRC, inverted to guarantee an invalid CRC upon reception. A signal is sent to the system indicating
that a collision occurred and that the start of the frame is needed for retransmission. The eTSEC then backs
off of the medium for a time determined by the truncated binary exponential back off (BEB) algorithm.
Following this back-off time, the packet is retried. The back-off time can be skipped if configured through
the half-duplex register. However, this is non-standard behavior and its use must be carefully applied.
Should any one packet experience excessive collisions, the packet is aborted. The system should flush the
frame and move to the next one in line. If the system requests to send a packet while the eTSEC is deferring
to a carrier, the eTSEC simply waits until the end of the carrier event and the timing of IPG before it honors
the request.
If packet transmission attempts experience collisions, the eTSEC outputs the jam sequence and waits some
amount of time before retrying the packet. This amount of time is determined by a controlled
randomization process called truncated binary exponential back-off. The amount of time is an integer
number of slot times. The number of slot times to delay before the nth retransmission attempt is chosen as
a uniformly-distributed random integer r in the range:
0  r  2
k
, where k = min(n,10).
So after the first collision, the eTSEC backs off either 0 or 1 slot times. After the fifth collision, the eTSEC
backs off between 0 and 32 slot times. After the tenth collision, the maximum number of slot times to back
off is 1024. This can be adjusted through the half-duplex register. An alternate truncation point, such as 7
for instance, can be programmed. On average, the MAC is more aggressive after seven collisions than
other stations on the network.