Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-61
Table 16-37 describes the fields of the RBASEn registers.
16.5.3.3.12 Receive Stamp Register (TMR_RXTS_H/L)
Receive time stamp register (RXTS_H/L). This register holds the value present in TMR_CNT_H/L when
the eTSEC detects a new incoming Ethernet frame. This register is only updated when the precision time
stamp logic is enable via TMR_CTRL[TE]. This register is read only in normal operation. Figure 16-34
describes the definition for the RXTS_H/L register.
Table 16-38 describes the fields of the TMR_RXTS_H/L register.
16.5.3.4 MAC Functionality
This section describes the MAC registers and provides a brief overview of the functionality that can be
exercised through the use of these registers, particularly those that provide functionality not explicitly
required by the IEEE 802.3 standard. All of the MAC registers are 32 bits wide.
16.5.3.4.1 Configuring the MAC
The MAC configuration registers 1 and 2 provide for configuring the MAC in multiple ways:
• Adjusting the preamble length—The length of the preamble can be adjusted from the nominal
seven bytes to some other (non-zero) value. Should custom preamble insertion/extraction be
configured, then this register must by left at its default value.
• Varying pad/CRC combinations—Three different pad/CRC combinations are provided to handle a
variety of system requirements. Simplest are frames that already have a valid frame check
sequence (FCS) field. The other two options include appending a valid CRC or padding and then
appending a valid CRC, resulting in a minimum frame of 64 octets. In addition to the
Table 16-37. RBASE0–RBASE7 Field Descriptions
Bits Name Description
0–28 RBASEn Receive base for ring n. RBASE defines the starting location in the memory map for the eTSEC RxBDs.
This field must be 8-byte aligned. Together with setting the W (wrap) bit in the last BD, the user can select
how many BDs to allocate for the receive packets. The user must initialize RBASE before enabling the
eTSEC receive function on the associated ring.
29–31 — Reserved
Offset eTSEC1:0x2_44C4; eTSEC2:0x2_54C4 Access: Read/Write
03132 63
R
TMR_RXTS_H
TMR_RXTS_L
W
Reset All zeros
Figure 16-34. TMR_RXTS_H/L Register Definition
Table 16-38. TMR_RXTS_H/L Register Field Descriptions
Bits Name Description
0–63 TMR_RXTS_H/L Value of the eTSEC precision timer upon detection of a start of frame symbol for the received frame.