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Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-55
16.5.3.3.8 Receive Queue Filer Table Property Register (RQFPR)
RQFPR (see Figure 16-29) is accessed to read or write the RQPROP words in entries of the receive queue
filer table. The table entries are described in greater detail in Section 16.6.4.2, “Receive Queue Filer.” The
word accessed through RQFPR is defined by the current value of RQFAR. Figure 16-29 and Figure 16-30
describe the fields of the RQFPR register according to property ID.
22 CLE Cluster entry/exit (used in combination with AND bit). This bit brackets clusters, marking the start and end
entries of a cluster. Clusters cannot be nested.
0 Regular RQCTRL entry.
1 If entry matches and AND = 1, treat subsequent entries as belonging to a nested cluster and enter the
cluster; otherwise skip all entries up to and including the next cluster exit. If AND = 0, exit current cluster.
23 REJ Reject frame. This bit and its specified action are ignored if AND = 1.
0 If entry matches, accept frame and file it to RxBD ring Q.
1 If entry matches, reject frame and discard it, ignoring Q.
24 AND Match this entry and the next entry as a pair.
0 Match property[PID] against RQPROP, independent of the next entry.
1 Match property[PID] against RQPROP. If matched and CLE = 0, attempt to match next entry, otherwise,
skip all entries up to and including the entry with AND = 0. If matched and CLE = 1, enter cluster of entries,
otherwise, skip all entries up to and including the entry with CLE = 1 (cluster exit).
25–26 CMP Comparison operation to perform on the RQPROP entry at this index when PID > 0. The property value
extracted by the frame parser is masked by the 32-bit mask_register prior to comparison against RQPROP.
However, the property value is not permanently altered by the value in mask_register. By default,
mask_register is initialized to 0xFFFF_FFFF before each frame is processed.
In the case where PID = 0, CMP is interpreted as follows:
00/01 Filer mask_register is set to all 32 bits of RQPROP, and this entry always matches.
10/11 Filer mask_register is set to all 32 bits of RQPROP, and this entry always fails to match.
In the case where PID > 0, CMP is interpreted as follows (& is bit-wise AND operator):
00 property[PID] & mask_register =RQPROP
01 property[PID] & mask_register  RQPROP
10 property[PID] & mask_register != RQPROP
11 property[PID] & mask_register <RQPROP
27 — Reserved, should be written with zero.
28–31 PID Property identifier. The value in the RQPROP entry at this index is interpreted according to PID (see
Table 16-34).
Offset eTSEC1:0x2_433C; eTSEC2:0x2_533C Access: Read/Write
0 31
R
RQPROP
W
Reset (undefined)
Figure 16-29. Receive Queue Filer Table Property IDs 0, 2–15 Register Definition
Table 16-33. RQFCR Field Descriptions (continued)
Bit Name Description