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Enhanced Three-Speed Ethernet Controllers

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

16-54 Freescale Semiconductor

Table 16-32 describes the fields of the RQFAR register.

16.5.3.3.7 Receive Queue Filer Table Control Register (RQFCR)

RQFCR is accessed to read or write the RQCTRL words in entries of the receive queue filer table. The

table entries are described in greater detail in Section 16.6.4.2, “Receive Queue Filer.” The word accessed

through RQFCR is defined by the current value of RQFAR.

Figure 16-28 describes the definition for the RQFCR register.

Table 16-33 describes the fields of the RQFCR register.

Offset eTSEC1:0x2_4334; eTSEC2:0x2_5334 Access: Read/Write

0 23 24 31

—RQFAR

Reset All zeros

Figure 16-27. Receive Queue Filer Table Address Register Definition

Table 16-32. RQFAR Field Descriptions

Bits Name Description

0–23 — Reserved

24–31 RQFAR Current index of receive queue filer table, which spans a total of 256 entries.

Offset eTSEC1:0x2_4338; eTSEC2:0x2_5338 Access: Read/Write

0 1 15 16 21 22 23 24 25 26 27 28 31

GPI — Q CLE REJ AND CMP — PID

Reset (undefined)

Figure 16-28. Receive Queue Filer Table Control Register Definition

Table 16-33. RQFCR Field Descriptions

Bit Name Description

0 GPI General purpose interrupt. When a property matches the value in the RQPROP entry at this index, and

REJ = 0 and AND = 0, the filer will instruct the Rx descriptor controller to set IEVENT[FGPI] when the

corresponding receive frame is written to memory.

If the timer is enabled (TMR_CTRL[TE] = 1), then TMR_PEVENT[RXP] will also be set.

1–15 — Reserved, should be written with zero.

16–21 Q Receive queue index, from 0 to 63, inclusive, written into the Rx frame control block associated with the

received frame. When a property matches the value in the RQPROP entry at this index, and REJ = 0 and

AND = 0, the frame is sent to either RxBD ring 0 (if RCTRL[FSQEN] = 1) or the RxBD ring with index (Q mod

8) and the filing table search is terminated. In the case where RCTRL[FSQEN] = 0, 8 virtual receive queues

are overlaid on every RxBD ring, and software needs to consult the RQ field of the Rx frame control block to

determine which virtual receive queue was chosen.