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Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-51
Table 16-29 describes the fields of the RXIC register.
16.5.3.3.4 Receive Queue Control Register (RQUEUE)
The RQUEUE register enables each of the RxBD rings 0–7. By default, RxBD ring 0 is enabled.
Figure 16-25 describes the definition for the RQUEUE register.
Table 16-30 describes the RQUEUE register.
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Table 16-29. RXIC Field Descriptions
Bits Name Description
0 ICEN Interrupt coalescing enable
0 Interrupt coalescing is disabled. Interrupts are raised as they are received.
1 Interrupt coalescing is enabled. If the eTSEC receive frame interrupt is enabled (IMASK[RXFEN] is set),
an interrupt is raised when the threshold number of frames is reached (defined by RXIC[ICFT]) or when
the threshold timer expires (determined by RXIC[ICTT]).
1 ICCS Interrupt coalescing timer clock source.
0 The coalescing timer advances count every 64 eTSEC Rx interface clocks (TSECn_GTX_CLK).
1 The coalescing timer advances count every 64 system clocks. This mode is recommended for FIFO
operation.
2—Reserved
3–10 ICFT Interrupt coalescing frame count threshold. While interrupt coalescing is enabled (RXIC[ICE] is set), this value
determines how many frames are received before raising an interrupt. The eTSEC threshold counter is reset
to ICFT following an interrupt. The value of ICFT must be greater than zero avoid unpredictable behavior.
11–15 — Reserved
16–31 ICTT Interrupt coalescing timer threshold. While interrupt coalescing is enabled (RXIC[ICE] is set), this value
determines the maximum amount of time after receiving a frame before raising an interrupt. If frames have
been received but the frame count threshold has not been met, an interrupt is raised when the threshold timer
reaches zero. The threshold timer is reset to the value in this field and begins counting down upon receiving
the first frame having its RxBD[I] bit set. The threshold value is represented in units equal to 64 periods of the
clock specified by RXIC[ICCS]. ICTT must be greater than zero to avoid unpredictable behavior.
Offset eTSEC1:0x2_4314; eTSEC2:0x2_5314 Access: Read/Write
0 7 8 9 10 11 12 13 14 15 16 23 24 25 26 27 28 29 30 31
R
— EX0 EX1 EX2 EX3 EX4 EX5 EX6 EX7 — EN0 EN1 EN2 EN3 EN4 EN5 EN6 EN7
W
Reset00000000 1 0 0 0 0 0 0 0 0 000000 0 1 0 0 0 0 0 0 0
Figure 16-25. RQUEUE Register Definition
Table 16-30. RQUEUE Field Descriptions
Bits Name Description
0–7 — Reserved
8–15 EXn Receive queue n extract enable.
0 Data transferred by DMA to this RxBD ring is not extracted to cache.
1 Data transferred by DMA to this RxBD ring undergoes extraction according to ATTR register.