Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-49
Writing 1 to any bit of this register clears it. Software should clear the QHLT bit to take eTSEC’s receiver
function out of halt state for the associated queue. Figure 16-23 describes the definition for the RSTAT
register.
Table 16-28 describes the fields of the RSTAT register.
Offset eTSEC1:0x2_4304; eTSEC2:0x2_5304 Access: w1c
0 7 8 9 10 11 12 13 14 15
R
—
QHLT0 QHLT1 QHLT2 QHLT3 QHLT4 QHLT5 QHLT6 QHLT7
W w1c w1c w1c w1c w1c w1c w1c w1c
Reset All zeros
16 23 24 25 26 27 28 29 30 31
R
—
RXF0 RXF1 RXF2 RXF3 RXF4 RXF5 RXF6 RXF7
W w1c w1c w1c w1c w1c w1c w1c w1c
Reset All zeros
Figure 16-23. RSTAT Register Definition
Table 16-28. RSTAT Field Descriptions
Bits Name Description
0–7 — Reserved
8 QHLT0 RxBD queue 0 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
not cause a QHLT0 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
9 QHLT1 RxBD queue 1 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
not cause a QHLT1 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
10 QHLT2 RxBD queue 2 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
not cause a QHLT2 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
11 QHLT3 RxBD queue 3 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
not cause a QHLT3 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.
12 QHLT4 RxBD queue 4 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does
not cause a QHLT4 to be set.). The current frame and all other frames directed to a halted queue are
discarded. A write with a value of 1 re-enables the queue for receiving.
0 This queue is enabled for reception. (That is, it is not halted)
1 All controller receive activity to this queue is halted.