Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-48 Freescale Semiconductor
16.5.3.3.2 Receive Status Register (RSTAT)
The eTSEC writes to this register under the following conditions:
• A frame interrupt event occurred on one or more RxBD rings
• The receiver runs out of descriptors due to a busy condition on a RxBD ring
• The receiver was halted because an error condition was encountered while receiving a frame
22 IPCSEN IP Checksum verification enable. See Section 16.6.3.3, “Receive Path Off-Load.”
0 IPv4 header checksums are not verified by the eTSEC—even if layer 3 parsing is enabled.
1 Perform IPv4 header checksum verification if PRSDEP > 01.
23 TUCSEN TCP or UDP Checksum verification enable. See Section 16.6.3.3, “Receive Path Off-Load.”
0 TCP or UDP checksums are not verified by the eTSEC—even if layer 4 parsing is enabled.
1 Perform TCP or UDP checksum verification if PRSDEP = 11.
24–25 PRSDEP Parser control. The level of parser layer recognition is determined as follows:
00 Parser disabled. Receive frame filer must also be disabled by clearing RCTRL[FILREN].
01 Only L2 (Ethernet) protocols are recognized.
10 L2 and L3 (IP) protocols are recognized.
11 L2, L3, and L4 (TCP/UDP) protocols are recognized.
If this field is non-zero, a TOE frame control block is prepended to the received frame, and the first RxBD
points to the FCB.
Note that if PRSDEP is cleared, VLEX must be cleared as well. (VLAN tag extraction is only supported
when the parser is enabled.) Also, if PRSDEP is cleared, FILREN must also be cleared.
26 — Reserved
27 BC_REJ Broadcast frame reject. If this bit is set, frames with DA (destination address) = FFFF_FFFF_FFFF are
rejected unless RCTRL[PROM] is set. If both BC_REJ and RCTRL[PROM] are set, then frames with
broadcast DA are accepted and the M (MISS) bit is set in the receive BD.
28 PROM Promiscuous mode. All Ethernet frames, regardless of destination address, are accepted.
29 RSF Receive short frame mode. When set, enables the reception of frames shorter than 64 bytes.
0 Ethernet frames less than 64 bytes in length are silently dropped.
1 Frames more than 16 bytes and less than 64 bytes in length are accepted upon a DA match.
Note that frames less than or equal to 16 bytes in length are always silently dropped.
30 EMEN Exact match MAC address enable. If this bit is set, the MAC01ADDR1–MAC15ADDR1 and
MAC01ADDR2–MAC15ADDR2 registers are recognized as containing MAC addresses aliasing the
MAC’s station address. Setting this bit therefore allows eTSEC to receive Ethernet frames having a
destination address matching one of these 15 addresses.
31 — Reserved
Table 16-27. RCTRL Field Descriptions (continued)
Bits Name Description