Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-47
Table 16-27 describes the fields of the RCTRL register.
Table 16-27. RCTRL Field Descriptions
Bits Name Description
0–6 — Reserved
7 TS Time stamp incoming packets as padding bytes. PAL field is set to 8 if the PAL field is programmed to less
than 8. Must be set to zero if TMR_CTRL[TE]=0.
8–10 — Reserved
11–15 PAL Packet alignment padding length. If not zero, PAL (1–31) bytes of zero padding are inserted before the
start of each received frame, but following the RxFCB if TOE is enabled. For Ethernet where optional
preamble extraction is enabled, the padding appears before the preamble, otherwise the padding
precedes the layer 2 header. The value of PAL can be set so that the start of the IP header in the receive
data buffer is aligned to a 32-bit boundary. Normally, setting PAL = 2 provides minimal padding to ensure
such alignment of the IP header.Note that the minimum zero padding value for this field should be PAL–8
if the TS field is set and 0 when PAL is < 8.
16 — Reserved
17 LFC Lossless flow control. When set, the eTSEC determines the number of free BDs (through RQPARMn[LEN]
and RBTPTRn) in each active ring. Should the free BD count in an active ring drop below its setting for
RQPARMn[FBTHR], the eTSEC asserts link layer flow control.
For full-duplex ethernet connections, the eTSEC emits a pause frame as if TCTRL[TFC_PAUSE] was set.
For FIFO packet interface connections, the RFC signal is asserted.
0 Disabled. This is the default
1 Enabled, calculate the free BDs in each active ring and assert link layer flow control if required.
18 VLEX Enable automatic VLAN tag extraction and deletion from Ethernet frames. Note that VLEX must be
cleared if L2OFF is non-zero.
0 Do not delete VLAN tags from received Ethernet frames.
1 If a VLAN tag is seen after the Ethernet source address, and PRSDEP is non-zero, delete the VLAN
tag and return the VLAN control word in the frame control block returned with this frame.
Note that if PRSDEP is cleared, VLEX must be cleared as well. (VLAN tag extraction is only supported
when the parser is enabled.)
19 FILREN Filer enable. When set, the receive frame filer is enabled. This file accepted frames to a particular RxBD
ring according to rules defined in the filer table. In this case, PRSDEP must not be cleared.
0 Do not search the receive queue filer table for received frames. All received frames are sent to RxBD
ring 0 by default.
1 Search the receive queue filer table for received frames, and let the filer determine the index of the
RxBD ring for each frame.
Note that if PRSDEP is cleared, FILREN must be cleared as well.
20 FSQEN Enable single-queue mode for the receive frame filer. This bit is ignored unless FILREN is also set.
0 The filer chooses the RxBD ring using the least significant bits of the virtual queue ID as a ring index.
1 The filer always attempts to file received frames to ring 0, regardless of virtual queue ID. This mode is
intended for operating the filer as a packet classification engine.
21 GHTX Group address hash table extend. By default, the group address hash table is 256 entries (as defined by
registers GADDR0–GADDR7); registers IGADDR0–IGADDR7 are then used to define the individual
address hash table. When this bit is set, the hash table is extended to a total of 512 entries
(IGADDR0–IGADDR7 are then the first 256 entries of the extended 512-entry group address hash table).
0 Both the individual and group hash functions are the 8 MSBs of the CRC-32 of the Ethernet destination
address.
1 The group hash function is the 9 MSBs of the CRC-32 of the Ethernet destination address. The
individual address hash function is unavailable.