Information
Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-46 Freescale Semiconductor
16.5.3.2.11 Transmit Time Stamp Register (TMR_TXTS1–2_H/L)
Transmit stamp register (TMR_TXTSn_H/L). This register holds the value of the TMR_CNT_H/L when
a frame tagged for timestamp capture (via Tx FCB[PTP]) is transmitted. Upon transmission of the start of
frame symbol of such a frame, the value in TMR_CNT_H/L is copied into TMR_TXTSn_H/L.
This register is read only in normal operation. Figure 16-21 depicts TMR_TXTSn_H/L.
Table 16-26 describes the fields of the TMR_TXTSn_H/L register.
16.5.3.3 eTSEC Receive Control and Status Registers
This section describes the control and status registers that are used specifically for receiving Ethernet
frames. All of the registers are 32 bits wide.
16.5.3.3.1 Receive Control Register (RCTRL)
The RCTRL register is programmed by the user and controls the operational mode of the receiver. It must
be written only after a system reset (at initialization) or after a graceful receive stop has completed.
Figure 16-22 describes the RCTRL register.
Offset eTSEC1:0x2_42C0+8n; eTSEC2:0x2_52C0+8n Access: Read only
0313263
R TXTS_H TXTS_L
W
Reset All zeros
Figure 16-21. TMR_TXTSn_H/L Register Definition
Table 16-26. TMR_TXTSn_H/L Register Field Descriptions
Bits Name Description
0–63 TXTS_H/L Time stamp field of the transmitted PTP packet’s start of frame detection.
Offset eTSEC1:0x2_4300; eTSEC2:0x2_5300 Access: Read/Write
0 6 7 8 10 11 15
R
—TS—PAL
W
Reset All zeros
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
— LFC VLEX FILREN FSQEN GHTX IPCSEN TUCSEN PRSDEP — BC_REJ PROM RSF EMEN —
W
Reset All zeros
Figure 16-22. RCTRL Register Definition