Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-44 Freescale Semiconductor
Table 16-22 describes the fields of the TR47WT register.
16.5.3.2.8 Transmit Buffer Descriptor Pointers 0–7 (TBPTR0–TBPTR7)
TBPTR0–TBPTR7 each contains the low-order 32 bits of the next transmit buffer descriptor address for
their respective TxBD ring. Figure 16-18 describes the TBPTR registers. These registers takes on the value
of their ring’s associated TBASE when the TBASE register is written by software. Software must not write
TBPTR0–TBPTR7 while eTSEC is actively transmitting frames. However, TBPTR0–TBPTR7 can be
modified when the transmitter is disabled or when no Tx buffer is in use (after a GRACEFUL STOP
TRANSMIT command is issued and the frame completes its transmission) in order to change the next
TxBD eTSEC transmits.
Table 16-23 describes the fields of the TBPTRn register.
Table 16-22. TR47WT Field Descriptions
Bits Name Description
0–7 WT4 Weighting value for TxBD ring 4 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT4  64 bytes of data are scheduled for transmission from TxBD ring 4. Clearing this field
prevents transmission.
8–15 WT5 Weighting value for TxBD ring 5 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT5  64 bytes of data are scheduled for transmission from TxBD ring 5. Clearing this field
prevents transmission.
16–23 WT6 Weighting value for TxBD ring 6 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT6  64 bytes of data are scheduled for transmission from TxBD ring 6. Clearing this field
prevents transmission.
24–31 WT7 Weighting value for TxBD ring 7 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a
minimum of WT7  64 bytes of data are scheduled for transmission from TxBD ring 7. Clearing this field
prevents transmission.
Offset eTSEC1:0x2_4184+8n; eTSEC2:0x2_5184+8n Access: Read/Write
0 28 29 31
R
TBPTRn —
W
Reset All zeros
Figure 16-18. TBPTR0–TBPTR7 Register Definition
Table 16-23. TBPTRn Field Descriptions
Bits Name Description
0–28 TBPTRn Current TxBD pointer for TxBD ring n. Points to the current BD being processed or to the next BD the
transmitter uses when it is idling. When the end of the TxBD ring is reached, eTSEC initializes TBPTRn to
the value in the corresponding TBASEn. The TBPTR register is internally written by the eTSEC’s DMA
controller during transmission. The pointer increments by eight (bytes) each time a descriptor is closed
successfully by the eTSEC. Note that the three least significant bits of this register are read-only and zero.
After an error condition, the eTSEC returns TBPTRn to point to the first BD of the frame partially transmitted.
29–31 — Reserved