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Enhanced Three-Speed Ethernet Controllers

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

Freescale Semiconductor 16-41

16.5.3.2.4 Transmit Interrupt Coalescing Register (TXIC)

The TXIC register enables and configures the operational parameters for interrupt coalescing associated

with transmitted frames. Figure 16-14 describes the definition for the TXIC register.

Table 16-19 describes the fields of the TXIC register.

Offset eTSEC1:0x2_4110; eTSEC2:0x2_5110 Access: Read/Write

0 1 2 3 10 11 15 16 31

ICEN ICCS — ICFT — ICTT

Reset All zeros

Figure 16-14. TXIC Register Definition

Table 16-19. TXIC Field Descriptions

Bits Name Description

0 ICEN Interrupt coalescing enable

0 Interrupt coalescing is disabled. Interrupts are raised as they are received.

1 Interrupt coalescing is enabled. If the eTSEC transmit frame interrupt is enabled (IMASK[TXFEN] is set),

an interrupt is raised when the threshold number of frames is reached (defined by TXIC[ICFT]) or when the

threshold timer expires (determined by TXIC[ICTT]).

1 ICCS Interrupt coalescing timer clock source.

0 The coalescing timer advances count every 64 eTSEC Tx interface clocks (TSECn_GTX_CLK).

1 The coalescing timer advances count every 64 system clocks. This mode is recommended for FIFO

operation.

2—Reserved

3–10 ICFT Interrupt coalescing frame count threshold. While interrupt coalescing is enabled (TXIC[ICEN] is set), this

value determines how many frames are transmitted before raising an interrupt. The eTSEC threshold counter

is reset to ICFT following an interrupt. The value of ICFT must be greater than zero to avoid unpredictable

behavior.

11–15 — Reserved

16–31 ICTT Interrupt coalescing timer threshold. While interrupt coalescing is enabled (TXIC[ICEN] is set), this value

determines the maximum amount of time after transmitting a frame before raising an interrupt. If frames have

been transmitted but the frame count threshold has not been met, an interrupt is raised when the threshold

timer reaches zero. The threshold timer is reset to the value in this field and begins counting down upon

transmission of the first frame having its TxBD[I] bit set. The threshold value is represented in units of 64 clock

periods as specified by the timer clock source (TXIC[ICCS[). The value of ICTT must be greater than zero to

avoid unpredictable behavior.