Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-36 Freescale Semiconductor
16.5.3.2.2 Transmit Status Register (TSTAT)
This register is read/write-one-to-clear and is written by the eTSEC to convey DMA status information for
each TxBD ring. The halt bit only has meaning for enabled rings. After processing transmit-related
interrupts, software should use TSTAT to restart transmission from rings that may have been affected by
the interrupt condition. In particular, an error condition that prevents eTSEC from continuing transmission
halts DMA from all rings, including the ring that gave rise to the error. Figure 16-12 describes the TSTAT
register.
Offset eTSEC1:0x2_4104; eTSEC2:0x2_5104 Access: w1c
012345678 15
R THLT0 THLT1 THLT2 THLT3 THLT4 THLT5 THLT6 THLT7
—
W w1c w1c w1c w1c w1c w1c w1c w1c
Reset All zeros
16 17 18 19 20 21 22 23 24 31
R TXF0 TXF1 TXF2 TXF3 TXF4 TXF5 TXF6 TXF7
—
W w1c w1c w1c w1c w1c w1c w1c w1c
Reset All zeros
Figure 16-12. TSTAT Register Definition