Information

Signal Descriptions
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
2-10 Freescale Semiconductor
LGPL0, LFCLE LBC UPM
general
purpose line 0,
Flash
command latch
enable
eLBC 1 O 10-2/10-5 — —
LGPL1, LFALE LBC GP line 1,
Flash address
latch enable
eLBC 1 O 10-2/10-5 — —
LGPL2, LOE, LFRE LBC GP line 2,
LBC output
enable, Flash
read enable
eLBC 1 O 10-2/10-5 — —
LGPL3, LFWP LBC GP line 3,
Flash write
protect
eLBC 1 O 10-2/10-5 — —
LGPL4, LGTA,
LUPWAIT, LFRB
LBC GP line 4,
Transaction
termination,
External device
wait, Flash
ready/busy
eLBC 1 I/O 10-2/10-5 — —
LGPL5 LBC GP line 5 eLBC 1 O 10-2/10-5 — —
LCLK0 LBC clock eLBC 1 O 10-2/10-5 — —
IIC_SDA1 I
2
C serial data 1 I
2
C 1 I/O 17-1/17-3 — —
IIC_SDA2 I
2
C serial data 2 I
2
C 1 I/O 17-1/17-3 CKSTOP_OUT —
IIC_SCL1 I
2
C serial clock
1
I
2
C 1 I/O 17-1/17-3 — —
IIC_SCL2 I
2
C serial clock
2
I
2
C 1 I/O 17-1/17-3 CKSTOP_IN —
UART_SOUT[1] DUART serial
data out
DUART 1 O 18-1/18-3 MSRCID0/LSRCID0 —,
10-2/10-5
UART_SOUT[2] DUART serial
data out
DUART 1 O 18-1/18-3 MSRCID2/LSRCID2 —,
10-2/10-5
UART_SIN[1] DUART serial
data in
DUART 1 I/O 18-1/18-3 MSRCID1/LSRCID1 —,
10-2/10-5
UART_SIN[2] DUART serial
data in
DUART 1 I/O 18-1/18-3 MSRCID3/LSRCID3 —,
10-2/10-5
SPIMOSI SPI master-out
slave-in
SPI 1 I/O 19-1/19-6 MSRCID4/LSRCID4 —,
10-2/10-5
SPIMISO SPI master-in
slave-out
SPI 1 I/O 19-1/19-6 MDVAL/LDVAL —,
10-2/10-5
Table 2-1. MPC8308 Signal Reference by Functional Block (continued)
Name Description
Functional
Block
No. of
Signals
I/O
Table/
Page
Alternate
Function(s)
Table/
Page