Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-35
18 TUCSEN TCP/UDP header checksum generation enable. When set, the eTSEC offloads TCP or UDP header
checksum generation. See Section 16.6.3.2, “Transmit Path Off-Load and Tx PTP Packet Parsing.”
0 TCP or UDP header checksum generation is disabled even if enabled in a transmit frame control block.
1 TCP or UDP header checksum generation is performed as determined by the settings in the current
transmit frame control block.
19 VLINS VLAN (IEEE Std. 802.1Q) tag insertion enable. Applicable only for transmission through the Ethernet
MAC.
0 Do not insert a VLAN tag into the frame.
1 Insert a VLAN tag into the frame. If the frame FCB has a valid VLAN field, use the FCB to source the
VLAN control word, otherwise take the default VLAN control word from register DFVLAN.
20 THDF Transmit half-duplex flow control under software control for 10-/100-Mbps half-duplex media. This bit is
not self-resetting.
0 Disable back pressure
1 Back pressure is applied to media by raising carrier
21–26 — Reserved
27 RFC_PAUSE Receive flow control pause frame (written by the eTSEC). This read-only status bit is set if a flow control
pause frame was received and the transmitter is paused for the duration defined in the received pause
frame. This bit automatically clears after the pause duration is complete.
0 Pause duration complete.
1 Flow control pause frame received.
28 TFC_PAUSE Transmit flow control pause frame. Set this bit to transmit a PAUSE frame. If this bit is set, the MAC stops
transmission of data frames after the currently transmitting frame completes. Next, the MAC transmits a
pause control frame with the duration value obtained from the PTV register. The TXC event occurs after
sending the pause control frame. Finally, the controller clears TFC_PAUSE and resumes transmitting
data frames as before. Note that pause control frames can still be transmitted if the Tx controller is
stopped due to user assertion of DMACTRL[GTS] or reception of a PAUSE frame.
0 No request for Tx PAUSE frame pending or transmission complete.
1 Software request for Tx PAUSE frame pending.
29–30 TXSCHED Transmit ring scheduling algorithm. This field determines which scheme the transmit scheduler uses to
arbitrate between the enabled TxBD rings. The scheme chosen also controls how the DMACTRL and
TQUEUE bits are interpreted. Ring polling is supported only by mode 00; the other modes require
software to restart rings with the TSTAT register. TCP/IP offload can be enabled with any scheduling
mode.
00 Single polled ring mode. TxBD ring 0 is the only ring serviced, even if other rings are enabled and
ready. In this scheduler mode, the DMACTRL[WOP] and DMACTRL[TOD] bits control polling and
retry behavior. This mode supports ring polling, and allows fetching of a non-ready TxBD to be retried
twice.
01 Priority scheduling mode. Frames from enabled TxBD rings are serviced in ascending ring index
order.
10 Modified weighted round-robin scheduling mode. Each TxBD ring is polled in sequence for frames
that are ready for transmission. If a non-ready TxBD is fetched from a ring, that ring is removed from
the scheduling pool until software re-enables it. Ready frames are repeatedly transmitted from a
chosen ring until its transmission quota is exhausted. The transmission quota for TxBD ring n is set
to WTn  64 bytes, where WTn is a weight from the TR03WT/TR47WT registers. If a ring transmits
more data than its quota allows, the excess is deducted from its quota on the next transmission
opportunity, thereby preventing large frames from monopolizing the eTSEC bandwidth.
11 Reserved
31 — Reserved
Table 16-16. TCTRL Field Descriptions (continued)
Bits Name Description