Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-34 Freescale Semiconductor
Table 16-15 describes the fields of the TBIPA register.
16.5.3.2 eTSEC Transmit Control and Status Registers
This section describes the control and status registers that are used specifically for transmitting Ethernet
frames. All of the registers are 32 bits wide.
16.5.3.2.1 Transmit Control Register (TCTRL)
This register is writable by the user to configure the transmit block. Figure 16-11 describes the TCTRL
register.
Table 16-16 describes the fields of the TCTRL register.
Offset eTSEC1:0x2_4030; eTSEC2:0x2_5030 Access: Mixed
0 26 31
R
—TBIPA
W
Reset All zeros
Figure 16-10. TBIPA Register Definition
Table 16-15. TBIPA Field Descriptions
Bits Name Description
0–26 — Reserved
27–31 TBIPA This field holds the PHY address of the MII management interface.
Note: The value of 0 is reserved. External PHY cannot have the address 0.
Offset eTSEC1:0x2_4100; eTSEC2:0x2_5100 Access: Mixed
0161718192021262728293031
R
— IPCSEN TUCSEN VLINS THDF —
RFC_PAUSE
TFC_PAUSE TXSCHED —
W
Reset All zeros
Figure 16-11. TCTRL Register Definition
Table 16-16. TCTRL Field Descriptions
Bits Name Description
0–16 — Reserved
17 IPCSEN IP header checksum generation enable. When set, the eTSEC offloads IPv4 header checksum
generation. See Section 16.6.3.2, “Transmit Path Off-Load and Tx PTP Packet Parsing.”
0 IP header checksum generation is disabled even if enabled in a transmit frame control block.
1 IP header checksum generation is performed for IPv4 headers as determined by the settings in the
current transmit frame control block.